thoughtpolice / yosys-bluespecLinks
Yosys plugin for synthesis of Bluespec code
☆15Updated 4 years ago
Alternatives and similar repositories for yosys-bluespec
Users that are interested in yosys-bluespec are comparing it to the libraries listed below
Sorting:
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 7 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Mutation Cover with Yosys (MCY)☆87Updated last week
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- RISC-V BSV Specification☆21Updated 5 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆33Updated this week
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Hardware generator debugger☆76Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆13Updated 8 years ago
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- chipy hdl☆17Updated 7 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- Verilog based simulation modell for 7 Series PLL☆17Updated 5 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- PicoRV☆43Updated 5 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago