thoughtpolice / yosys-bluespecLinks
Yosys plugin for synthesis of Bluespec code
☆15Updated 4 years ago
Alternatives and similar repositories for yosys-bluespec
Users that are interested in yosys-bluespec are comparing it to the libraries listed below
Sorting:
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 2 weeks ago
- RISC-V BSV Specification☆22Updated 5 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆88Updated this week
- Libre Silicon Compiler☆22Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Board and connector definition files for nMigen☆30Updated 5 years ago
- PicoRV☆43Updated 5 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- Industry standard I/O for nMigen☆12Updated 5 years ago
- Hardware generator debugger☆77Updated last year
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- Example of how to use UVM with Verilator☆25Updated 3 weeks ago
- A Verilog Synthesis Regression Test☆37Updated last year
- chipy hdl☆17Updated 7 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆13Updated 8 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 6 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 7 years ago
- ☆27Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆33Updated last week
- Industry standard I/O for Amaranth HDL☆30Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago