thoughtpolice / yosys-bluespec
Yosys plugin for synthesis of Bluespec code
☆15Updated 3 years ago
Alternatives and similar repositories for yosys-bluespec:
Users that are interested in yosys-bluespec are comparing it to the libraries listed below
- RISC-V BSV Specification☆20Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 2 weeks ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 3 weeks ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Libre Silicon Compiler☆23Updated 3 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Small footprint and configurable HyperBus core☆11Updated 2 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 3 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆16Updated 3 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆28Updated last week
- Mutation Cover with Yosys (MCY)☆80Updated 3 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 6 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- chipy hdl☆17Updated 6 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Open SoC Debug Hardware Reference Implementation☆16Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- An FPGA reverse engineering and documentation project☆41Updated this week
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆13Updated 5 years ago
- PicoRV☆44Updated 5 years ago
- 32-bit RISC-V Emulator☆23Updated 6 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 2 weeks ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- Finding the bacteria in rotting FPGA designs.☆13Updated 4 years ago
- ☆23Updated 3 years ago