Alternatives and similar repositories for yosys-bluespec

Users that are interested in yosys-bluespec are comparing it to the libraries listed below

• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆22Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated this week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated last week
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 10 months ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago
• m-labs / nmigen-stdio
  Industry standard I/O for nMigen
  ☆12Updated 5 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• benpye / nix-fpga-tools
  ☆27Updated 3 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆41Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 7 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 8 years ago
• CTSRD-CHERI / BlueStuff
  A Bluespec SystemVerilog library of miscellaneous components
  ☆18Updated 7 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• nmi-leipzig / sim-x-pll
  Verilog based simulation modell for 7 Series PLL
  ☆17Updated 5 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆27Updated last month
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆28Updated 2 weeks ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated 3 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago