Block-diagram style digital logic visualizer
☆23Sep 16, 2015Updated 10 years ago
Alternatives and similar repositories for chisualizer
Users that are interested in chisualizer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A self-contained computer stack hobby project☆15Dec 23, 2016Updated 9 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- The specification for the FIRRTL language☆66Updated this week
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 6 years ago
- ☆85Jun 1, 2022Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆20Sep 26, 2024Updated last year
- ☆20Feb 9, 2020Updated 6 years ago
- MiMa Plugin for Mill☆17Jun 18, 2026Updated last month
- A curated list of amazingly DCjanus.☆16Jan 30, 2019Updated 7 years ago
- ☆27Sep 3, 2020Updated 5 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆65Jun 27, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- The home of the Chisel3 website☆21May 24, 2024Updated 2 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated 10 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated 10 months ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Mar 2, 2023Updated 3 years ago
- ☆61Jul 4, 2022Updated 4 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆92Jul 15, 2026Updated 2 weeks ago
- Wake build descriptions of hardware generators☆12Dec 11, 2020Updated 5 years ago
- LTE/WiFi/5G-NR SDR Transceiver☆56Dec 18, 2018Updated 7 years ago
- ☆17Jul 21, 2026Updated last week
- Python interface to FPGA interchange format☆41Oct 19, 2022Updated 3 years ago
- BSC Development Workstation (BDW)☆33May 1, 2026Updated 2 months ago
- high-performance RTL simulator☆195Updated this week