ducky64 / chisualizer
Block-diagram style digital logic visualizer
☆23Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for chisualizer
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- A Verilog Synthesis Regression Test☆34Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Debuggable hardware generator☆67Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- ☆18Updated 4 years ago
- The specification for the FIRRTL language☆46Updated this week
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Useful utilities for BAR projects☆30Updated 10 months ago
- A coverage library for Chisel designs☆11Updated 4 years ago
- Open Processor Architecture☆26Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- Chisel Cheatsheet☆31Updated last year
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- ☆33Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- ☆36Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- ☆52Updated 2 years ago
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago