A tool for merging the MyHDL workflow with Vivado
☆20May 13, 2020Updated 6 years ago
Alternatives and similar repositories for Ovenbird
Users that are interested in Ovenbird are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 13 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 4 months ago
- Wake build descriptions of hardware generators☆12Dec 11, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- A high throughput FFT implementation☆20Jan 17, 2022Updated 4 years ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Jan 22, 2026Updated 6 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 7 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 11 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆28Updated this week
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- FPGA raycaster engine written in verilog☆14Apr 19, 2019Updated 7 years ago
- Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.☆17May 3, 2016Updated 10 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- ☆27Sep 3, 2020Updated 5 years ago
- Python tools for Vivado Projects☆72Apr 3, 2019Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆73Jul 17, 2026Updated last week
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- The home of the Chisel3 website☆21May 24, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 5 months ago
- FPU Generator☆20Jul 16, 2026Updated last week
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Software control for CASPER FPGAs☆22Feb 5, 2026Updated 5 months ago
- A port of Lode's QuickCG library to SDL 2.0.☆13Mar 28, 2024Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated 2 years ago
- Cross EDA Abstraction and Automation☆42Nov 17, 2025Updated 8 months ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Minimal ncurses implementation for use in embedded environments☆12Oct 29, 2017Updated 8 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- Implementing the Double-Slit experiment in Python☆12Jan 7, 2021Updated 5 years ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 2 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- Yet another IPython notebook to LaTeX converter - this one exports clean code easily absorbed in other reports.☆16Jun 1, 2023Updated 3 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆92Jul 7, 2021Updated 5 years ago