lac-dcc / chimeraLinks
A tool for synthesizing Verilog programs
☆107Updated 2 months ago
Alternatives and similar repositories for chimera
Users that are interested in chimera are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆182Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆92Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆124Updated 2 weeks ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆146Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆237Updated last month
- SystemVerilog frontend for Yosys☆170Updated last week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆110Updated 2 weeks ago
- RISC-V Formal Verification Framework☆166Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions