Alternatives and similar repositories for chimera

Users that are interested in chimera are comparing it to the libraries listed below

• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆160Updated this week
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆254Updated 4 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆186Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆191Updated last week
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆177Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆135Updated last week
• pulp-platform / svase
  ☆33Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆117Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆95Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆65Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆79Updated 2 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆35Updated 7 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆55Updated 5 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆118Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆135Updated this week
• bsc-loca / sargantana
  ☆125Updated 5 months ago