lac-dcc / chimeraLinks
A tool for synthesizing Verilog programs
☆101Updated 3 weeks ago
Alternatives and similar repositories for chimera
Users that are interested in chimera are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆117Updated last week
- high-performance RTL simulator☆175Updated last year
- RISC-V Formal Verification Framework☆150Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 8 months ago
- SystemVerilog frontend for Yosys☆161Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆220Updated 2 weeks ago
- RISC-V Nox core☆68Updated 2 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆134Updated this week
- WAL enables programmable waveform analysis.☆155Updated 3 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆105Updated 4 months ago
- A SystemVerilog source file pickler.☆60Updated 11 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆183Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- Python wrapper for verilator model☆88Updated last year
- Hardware generator debugger☆76Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆214Updated this week
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆108Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆76Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- Generic Register Interface (contains various adapters)☆128Updated last month
- ☆32Updated 8 months ago
- Chisel RISC-V Vector 1.0 Implementation☆111Updated 3 weeks ago
- ☆108Updated last month
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago