Alternatives and similar repositories for chimera:

Users that are interested in chimera are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆68Updated last week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 6 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆84Updated this week
• pulp-platform / svase
  ☆31Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆53Updated 2 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆50Updated 11 months ago
• pulp-platform / cheshire-ihp130-o
  ☆31Updated 3 months ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 5 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆142Updated 2 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆38Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆120Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 5 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 9 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆51Updated last month
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated 11 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆78Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆72Updated last month
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆50Updated 4 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆42Updated 3 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆20Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 3 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆99Updated 9 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆98Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 3 months ago