fischermoseley / mantaLinks
A configurable and approachable tool for FPGA debugging and rapid prototyping.
☆144Updated 8 months ago
Alternatives and similar repositories for manta
Users that are interested in manta are comparing it to the libraries listed below
Sorting:
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- CoreScore☆171Updated last month
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- Example LED blinking project for your FPGA dev board of choice☆189Updated 2 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆252Updated last year
- Nix flake for openXC7☆44Updated 8 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆82Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 2 weeks ago
- Documenting Lattice's 28nm FPGA parts☆147Updated last year
- VHDL library 4 FPGAs☆184Updated this week
- Board definitions for Amaranth HDL☆121Updated 4 months ago
- ☆88Updated 2 months ago
- End-to-end synthesis and P&R toolchain☆93Updated 3 weeks ago
- Small footprint and configurable embedded FPGA logic analyzer☆198Updated 2 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆64Updated 8 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆75Updated 2 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆54Updated last month
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆186Updated last year
- Naive Educational RISC V processor☆93Updated 2 months ago
- assorted library of utility cores for amaranth HDL☆99Updated last year
- USB Serial on the TinyFPGA BX☆139Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- A configurable RTL to bitstream FPGA toolchain☆55Updated 2 weeks ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆211Updated last month
- The open-source Zynq 7000 BSP generator for openXC7☆49Updated 11 months ago
- Project X-Ray Database: XC7 Series☆73Updated 4 years ago