sld-columbia / esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
☆360Updated this week
Alternatives and similar repositories for esp:
Users that are interested in esp are comparing it to the libraries listed below
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆459Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆403Updated last month
- VeeR EL2 Core☆266Updated this week
- Common SystemVerilog components☆583Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆405Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆246Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆558Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 4 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆502Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- Instruction Set Generator initially contributed by Futurewei☆273Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆247Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆181Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆265Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆236Updated 4 months ago
- A Linux-capable RISC-V multicore for and by the world☆666Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆183Updated this week
- Bus bridges and other odds and ends☆523Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆246Updated 4 months ago
- CORE-V Family of RISC-V Cores☆239Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆230Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆222Updated 3 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆479Updated 3 months ago
- ☆309Updated 6 months ago
- ☆229Updated 2 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆244Updated 4 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆165Updated this week
- Build Customized FPGA Implementations for Vivado☆303Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆169Updated 2 years ago