scalesim-project / SCALE-SimLinks
Repository to host and maintain SCALE-Sim code
☆390Updated this week
Alternatives and similar repositories for SCALE-Sim
Users that are interested in SCALE-Sim are comparing it to the libraries listed below
Sorting:
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆243Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆152Updated 6 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆436Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆174Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆232Updated 3 years ago
- ☆371Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆147Updated 6 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A scalable High-Level Synthesis framework on MLIR☆285Updated last year
- An Automatic Synthesis Tool for PIM-based CNN Accelerators.☆16Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆174Updated 2 weeks ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 9 months ago
- Allo Accelerator Design and Programming Framework☆313Updated this week
- Processing-In-Memory (PIM) Simulator☆210Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated last month
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆106Updated 7 months ago
- Research and Materials on Hardware implementation of Transformer Model☆294Updated 9 months ago
- BookSim 2.0☆387Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆254Updated 3 years ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆517Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆104Updated last month
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- ☆115Updated last year
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆212Updated 2 years ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆110Updated 8 months ago
- ☆58Updated last year
- A co-design architecture on sparse attention☆54Updated 4 years ago