Accelergy-Project / accelergyLinks
Accelergy is an energy estimation infrastructure for accelerator energy estimations
☆154Updated 7 months ago
Alternatives and similar repositories for accelergy
Users that are interested in accelergy are comparing it to the libraries listed below
Sorting:
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 6 months ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆245Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- Repository to host and maintain SCALE-Sim code☆405Updated 3 weeks ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆113Updated 9 months ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆114Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- ☆42Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆68Updated 6 years ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆58Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- ☆80Updated last week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- A co-design architecture on sparse attention☆55Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31Updated 2 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- Simulator for BitFusion☆102Updated 5 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆107Updated 8 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 2 years ago