Alternatives and similar repositories for MAESTRO

Users that are interested in MAESTRO are comparing it to the libraries listed below

• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆72Updated 6 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆30Updated 6 years ago
• cucapra / fodlam
  first-order deep learning accelerator model
  ☆18Updated 7 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• sparsh0mittal / destiny_3d_cache
  Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…
  ☆23Updated 6 months ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆39Updated 6 years ago
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• maeri-project / mRNA
  mRNA
  ☆22Updated 4 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆103Updated 5 years ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• maestro-project / gamma
  ☆41Updated 11 months ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• hsharma35 / bitfusion
  Simulator for BitFusion
  ☆100Updated 4 years ago
• maestro-project / confuciux
  ☆33Updated 3 years ago
• hyoukjun / OpenSMART
  Public release
  ☆52Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• aravinds92 / Systolic-Array
  Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
  ☆12Updated 9 years ago