hyoukjun / MAESTROLinks
MAESTRO binary release
☆22Updated 5 years ago
Alternatives and similar repositories for MAESTRO
Users that are interested in MAESTRO are comparing it to the libraries listed below
Sorting:
- MAERI public release☆31Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- first-order deep learning accelerator model☆20Updated 7 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆24Updated 9 months ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- ☆72Updated 2 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Updated 3 years ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆180Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆24Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- ☆71Updated 5 years ago
- Simulator for BitFusion☆102Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago
- ☆10Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Public release☆56Updated 6 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆64Updated 2 weeks ago
- ☆35Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆33Updated 4 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆149Updated 4 months ago