hyoukjun / MAESTROLinks
MAESTRO binary release
☆22Updated 5 years ago
Alternatives and similar repositories for MAESTRO
Users that are interested in MAESTRO are comparing it to the libraries listed below
Sorting:
- MAERI public release☆31Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- Tool for optimize CNN blocking☆93Updated 5 years ago
- first-order deep learning accelerator model☆20Updated 7 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆180Updated last year
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆25Updated 10 months ago
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 8 months ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- ☆72Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆144Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆78Updated 6 years ago
- ☆27Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- ☆32Updated 4 years ago
- ☆35Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- Simulator for BitFusion☆102Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Explore the energy-efficient dataflow scheduling for neural networks.☆228Updated 5 years ago
- Public release☆56Updated 6 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 7 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago