maeri-project / FEATHERLinks
A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
☆54Updated 3 months ago
Alternatives and similar repositories for FEATHER
Users that are interested in FEATHER are comparing it to the libraries listed below
Sorting:
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated last week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- RTL implementation of Flex-DPE.☆106Updated 5 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆151Updated last week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆147Updated this week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆54Updated 2 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆49Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆144Updated last month
- ☆17Updated 2 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆71Updated last month
- MICRO22 artifact evaluation for Sparseloop☆45Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- ☆9Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆80Updated 11 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆133Updated 3 weeks ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆27Updated 5 months ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆98Updated 3 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- ☆49Updated 3 years ago
- ☆27Updated 3 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- ☆61Updated last month
- Implementation of Microscaling data formats in SystemVerilog.☆21Updated last week
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆26Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago