GATECH-EIC / AutoDNNchipLinks
☆71Updated 5 years ago
Alternatives and similar repositories for AutoDNNchip
Users that are interested in AutoDNNchip are comparing it to the libraries listed below
Sorting:
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- ☆71Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- ☆34Updated 4 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- Approximate layers - TensorFlow extension☆27Updated last month
- Simulator for BitFusion☆99Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆36Updated 4 years ago
- ☆41Updated 11 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆43Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆138Updated last week
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- ☆27Updated 2 months ago
- ☆33Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 6 years ago