Alternatives and similar repositories for rip:

Users that are interested in rip are comparing it to the libraries listed below

• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆25Updated 4 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 3 years ago
• icgrp / hipr
  ☆15Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆20Updated 2 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• priyanka-raina / dnn-accelerator
  ☆13Updated 4 years ago
• Blaok / soda
  Stencil with Optimized Dataflow Architecture
  ☆12Updated last year
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆14Updated 10 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• template-hls / template-hls-float
  ☆29Updated 5 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆27Updated last year
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• icgrp / pld2022
  ☆15Updated 2 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 7 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• chipsalliance / aib-protocols
  ☆25Updated last year
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated last year
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago