harvard-acc / EdgeBERT
HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
☆46Updated last year
Alternatives and similar repositories for EdgeBERT:
Users that are interested in EdgeBERT are comparing it to the libraries listed below
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆50Updated 3 weeks ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated last month
- ☆32Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆33Updated 6 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- ☆15Updated 3 years ago
- ☆25Updated 11 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆38Updated last year
- ☆20Updated 2 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- ☆26Updated 3 months ago
- ☆35Updated 3 years ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆34Updated last year
- ☆70Updated 5 years ago
- ☆43Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆30Updated this week
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆49Updated 2 weeks ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- Approximate layers - TensorFlow extension☆27Updated 11 months ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- ☆21Updated last month
- Eyeriss chip simulator☆36Updated 5 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆12Updated last year
- ☆14Updated last year