Accelergy-Project / micro22-sparseloop-artifactLinks
MICRO22 artifact evaluation for Sparseloop
☆44Updated 3 years ago
Alternatives and similar repositories for micro22-sparseloop-artifact
Users that are interested in micro22-sparseloop-artifact are comparing it to the libraries listed below
Sorting:
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last week
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆60Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆72Updated 5 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆41Updated last year
- ☆48Updated 2 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆97Updated 5 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆67Updated 3 weeks ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47Updated last year
- ☆48Updated 4 years ago
- A co-design architecture on sparse attention☆53Updated 4 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆76Updated 7 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆67Updated last month
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆86Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆35Updated 5 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆67Updated 2 years ago
- ☆28Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- STONNE: A Simulation Tool for Neural Networks Engines☆140Updated 4 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 10 months ago
- Tool for optimize CNN blocking☆93Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆150Updated 4 months ago