mRNA
☆27Mar 16, 2021Updated 5 years ago
Alternatives and similar repositories for mRNA
Users that are interested in mRNA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- ☆19Jun 17, 2022Updated 3 years ago
- ☆45Jun 30, 2024Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆250Apr 15, 2024Updated 2 years ago
- RTL implementation of Flex-DPE.☆116Feb 22, 2020Updated 6 years ago
- ☆74Mar 22, 2020Updated 6 years ago
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- ☆11Oct 28, 2021Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆86Aug 28, 2023Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Feb 8, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Jul 17, 2023Updated 2 years ago
- Fibertree emulator☆17Nov 4, 2024Updated last year
- FRAME: Fast Roofline Analytical Modeling and Estimation☆39Oct 13, 2023Updated 2 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog☆12Dec 26, 2020Updated 5 years ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆27Sep 21, 2021Updated 4 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- Release of stream-specialization software/hardware stack.☆123May 5, 2023Updated 2 years ago
- Architect's workbench☆10May 5, 2016Updated 9 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆80Updated this week
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators☆124Oct 26, 2022Updated 3 years ago
- Domain-Specific Architecture Generator 2☆24Oct 2, 2022Updated 3 years ago
- ☆14Oct 8, 2024Updated last year
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The code for paper: Neuralpower: Predict and deploy energy-efficient convolutional neural networks☆24Jul 10, 2019Updated 6 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- agile hardware-software co-design☆53Dec 12, 2021Updated 4 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17May 4, 2020Updated 5 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Jun 14, 2020Updated 5 years ago
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 6 years ago
- A graph linear algebra overlay☆52Apr 26, 2023Updated 3 years ago