maeri-project / mRNA
mRNA
☆22Updated 3 years ago
Alternatives and similar repositories for mRNA:
Users that are interested in mRNA are comparing it to the libraries listed below
- ☆16Updated 2 years ago
- ☆39Updated 7 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆25Updated 9 months ago
- Heterogenous ML accelerator☆17Updated 4 months ago
- ☆10Updated 4 months ago
- ☆32Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- ☆9Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆25Updated 3 years ago
- HW accelerator mapping optimization framework for in-memory computing☆21Updated last month
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated 3 weeks ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆28Updated 6 months ago
- ☆69Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆33Updated 4 years ago
- ☆23Updated 4 years ago
- ☆71Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆13Updated 4 months ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆13Updated 4 years ago
- ☆11Updated last year
- MAESTRO binary release☆22Updated 5 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆17Updated 6 months ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago