maeri-project / mRNALinks
mRNA
☆23Updated 4 years ago
Alternatives and similar repositories for mRNA
Users that are interested in mRNA are comparing it to the libraries listed below
Sorting:
- ☆16Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆41Updated last year
- ☆28Updated 3 years ago
- Heterogenous ML accelerator☆18Updated 2 months ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆33Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆45Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated 11 months ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Updated 4 years ago
- ☆71Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- ☆13Updated 2 years ago
- ☆35Updated 5 years ago
- ☆10Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated 2 years ago
- ☆28Updated 2 years ago
- ☆71Updated 5 years ago
- ☆16Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆20Updated last year
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆111Updated 2 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- NeuraChip Accelerator Simulator☆13Updated last year
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- ☆25Updated last year
- An HBM FPGA based SpMV Accelerator☆13Updated 10 months ago