maestro-project / AIrchitect-v2Links
[DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Representations
☆16Updated 7 months ago
Alternatives and similar repositories for AIrchitect-v2
Users that are interested in AIrchitect-v2 are comparing it to the libraries listed below
Sorting:
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆18Updated 2 years ago
- ☆28Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆35Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆72Updated 2 years ago
- ☆28Updated 2 years ago
- ☆12Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- Attentionlego☆12Updated last year
- ☆41Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- ☆10Updated 2 years ago
- ☆17Updated 3 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆62Updated 5 months ago
- An HBM FPGA based SpMV Accelerator☆13Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 4 months ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆25Updated last year
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆51Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆59Updated last week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆31Updated 9 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago