maestro-project / AIrchitect-v2Links
[DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Representations
☆14Updated 4 months ago
Alternatives and similar repositories for AIrchitect-v2
Users that are interested in AIrchitect-v2 are comparing it to the libraries listed below
Sorting:
- ☆18Updated 2 years ago
- ☆27Updated 2 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 10 months ago
- ☆12Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆10Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆36Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆9Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- ☆28Updated 2 years ago
- ☆22Updated 2 years ago
- ☆34Updated 4 years ago
- ☆26Updated 3 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆19Updated 9 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆27Updated last year
- ☆16Updated 3 weeks ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- Attentionlego☆12Updated last year
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated last year
- Open-source of MSD framework☆16Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- Heterogenous ML accelerator☆18Updated last month
- ☆33Updated 3 years ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆12Updated 3 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆12Updated 9 months ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago