casys-kaist / mNPUsimLinks
mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
☆55Updated 5 months ago
Alternatives and similar repositories for mNPUsim
Users that are interested in mNPUsim are comparing it to the libraries listed below
Sorting:
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆34Updated 5 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆67Updated 11 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆16Updated 2 months ago
- ☆32Updated 5 months ago
- Processing in Memory Emulation☆20Updated 2 years ago
- ☆69Updated 11 months ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆63Updated last month
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆52Updated 2 months ago
- ☆30Updated 2 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 5 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆17Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ☆12Updated last month
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆25Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆28Updated 2 years ago
- ☆29Updated 6 months ago
- ☆16Updated 2 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆118Updated 3 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆83Updated 11 months ago