casys-kaist / mNPUsimLinks
mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
☆66Updated last month
Alternatives and similar repositories for mNPUsim
Users that are interested in mNPUsim are comparing it to the libraries listed below
Sorting:
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆46Updated 4 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 7 months ago
- ☆50Updated this week
- ☆112Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆105Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆171Updated this week
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆44Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆96Updated last year
- ☆155Updated 10 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆60Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆38Updated 11 months ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆102Updated last year
- Processing in Memory Emulation☆22Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- ☆106Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆48Updated 3 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 8 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆21Updated 8 months ago
- ☆39Updated 8 months ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆111Updated 7 months ago
- ☆29Updated 4 years ago