linghaosong / SerpensLinks
An HBM FPGA based SpMV Accelerator
☆14Updated last year
Alternatives and similar repositories for Serpens
Users that are interested in Serpens are comparing it to the libraries listed below
Sorting:
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- HLS project modeling various sparse accelerators.☆11Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- NeuraChip Accelerator Simulator☆14Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- ☆16Updated 3 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆14Updated last year
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆21Updated last year
- ☆31Updated 10 months ago
- ☆16Updated 2 years ago
- ☆12Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆22Updated 10 months ago
- Processing in Memory Emulation☆21Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆25Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Updated 7 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- ☆16Updated 3 years ago