hsharma35 / bitfusionLinks
Simulator for BitFusion
☆102Updated 5 years ago
Alternatives and similar repositories for bitfusion
Users that are interested in bitfusion are comparing it to the libraries listed below
Sorting:
- Tool for optimize CNN blocking☆93Updated 5 years ago
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- ☆35Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆150Updated 5 months ago
- ☆32Updated 4 years ago
- ☆71Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- ☆111Updated last year
- ☆41Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last week
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆228Updated 5 years ago
- MNSIM_Python_v1.0. The former circuits-level version link: https://github.com/Zhu-Zhenhua/MNSIM_V1.1☆35Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆236Updated last year
- ☆48Updated 4 years ago
- Eyeriss chip simulator☆37Updated 5 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆144Updated 5 years ago
- A co-design architecture on sparse attention☆53Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- ☆29Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆52Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆67Updated last month
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆67Updated 2 years ago
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆23Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆142Updated 4 months ago