hsharma35 / bitfusionLinks
Simulator for BitFusion
☆102Updated 5 years ago
Alternatives and similar repositories for bitfusion
Users that are interested in bitfusion are comparing it to the libraries listed below
Sorting:
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- ☆35Updated 5 years ago
- ☆71Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆155Updated 8 months ago
- ☆42Updated last year
- ☆32Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆233Updated 5 years ago
- ☆72Updated 2 years ago
- Eyeriss chip simulator☆39Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆47Updated 3 years ago
- ☆48Updated 4 years ago
- MNSIM_Python_v1.0. The former circuits-level version link: https://github.com/Zhu-Zhenhua/MNSIM_V1.1☆35Updated 2 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆247Updated last year
- A co-design architecture on sparse attention☆55Updated 4 years ago
- ☆113Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- ☆29Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 4 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Updated 6 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆108Updated 9 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago