harvard-acc / smaug
SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
☆107Updated 2 years ago
Alternatives and similar repositories for smaug:
Users that are interested in smaug are comparing it to the libraries listed below
- STONNE: A Simulation Tool for Neural Networks Engines☆125Updated 9 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆174Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆230Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- gem5 repository to study chiplet-based systems☆70Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆134Updated last month
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆62Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆71Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆121Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆90Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆214Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆131Updated this week
- An integrated CGRA design framework☆87Updated 4 months ago
- ☆39Updated 8 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆141Updated 3 weeks ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 4 years ago
- ☆33Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- ☆29Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago