lulinchen / cnn_openLinks
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
☆238Updated 6 years ago
Alternatives and similar repositories for cnn_open
Users that are interested in cnn_open are comparing it to the libraries listed below
Sorting:
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- Implementation of CNN using Verilog☆224Updated 7 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- FPGA☆158Updated last year
- PYNQ学习资料☆164Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆183Updated 8 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- FPGA Accelerator for CNN using Vivado HLS☆319Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆151Updated 4 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆256Updated 7 years ago
- CNN acceleration on virtex-7 FPGA with verilog HDL☆457Updated 7 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆298Updated 4 months ago
- FPGA implementation of Cellular Neural Network (CNN)☆143Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- A convolutional neural network implemented in hardware (verilog)☆160Updated 7 years ago
- ☆278Updated last year
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆237Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- 中文:☆101Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆352Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一 层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆191Updated 9 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆157Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆67Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆116Updated 2 years ago