CodeNameGrapefruit / SoC_CNNLinks
Convolutional Neural Network Implemented in Verilog for System on Chip
☆27Updated 6 years ago
Alternatives and similar repositories for SoC_CNN
Users that are interested in SoC_CNN are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- ☆43Updated 4 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- ☆34Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated last year
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- AXI Interconnect☆52Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- ☆17Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Verification IP for APB protocol☆68Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago