CodeNameGrapefruit / SoC_CNNLinks
Convolutional Neural Network Implemented in Verilog for System on Chip
☆27Updated 6 years ago
Alternatives and similar repositories for SoC_CNN
Users that are interested in SoC_CNN are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated 11 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- ☆34Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆156Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated last year
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- AXI Interconnect☆51Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆43Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- ☆17Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆65Updated 6 years ago