CodeNameGrapefruit / SoC_CNN
Convolutional Neural Network Implemented in Verilog for System on Chip
☆23Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for SoC_CNN
- AXI Interconnect☆46Updated 3 years ago
- ☆26Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- An LeNet RTL implement onto FPGA☆39Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆32Updated 2 months ago
- AXI总线连接器☆91Updated 4 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- ☆16Updated 7 months ago
- ☆34Updated 9 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- ☆60Updated 5 years ago
- ☆16Updated 2 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆71Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago