Alternatives and similar repositories for groundhog

Users that are interested in groundhog are comparing it to the libraries listed below

• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆30Updated 9 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• FDU-ME-ARC / NVMeCHA
  ☆17Updated 4 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• ZipCPU / wbsata
  Wishbone SATA Controller
  ☆19Updated 3 months ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 4 months ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 3 weeks ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• mcrl / NVMe
  ☆32Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆35Updated 4 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• yhqiu16 / OCOWFC
  Open-Channel Open-Way Flash Controller
  ☆17Updated 4 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆26Updated 4 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 9 months ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 4 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago