fpgasystems / groundhogLinks
Groundhog - Serial ATA Host Bus Adapter
☆22Updated 7 years ago
Alternatives and similar repositories for groundhog
Users that are interested in groundhog are comparing it to the libraries listed below
Sorting:
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- ☆19Updated 4 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 9 months ago
- ☆33Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 2 months ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆16Updated 5 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆27Updated this week
- ☆17Updated 3 weeks ago
- Open-Channel Open-Way Flash Controller☆17Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- ☆73Updated 3 years ago
- Computational Storage Device based on the open source project OpenSSD.☆27Updated 4 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 8 months ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 6 months ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆16Updated 6 years ago
- ☆29Updated 4 years ago
- ☆31Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year