Alternatives and similar repositories for groundhog:

Users that are interested in groundhog are comparing it to the libraries listed below

• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• FDU-ME-ARC / NVMeCHA
  ☆14Updated 3 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆13Updated 6 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆22Updated last year
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆25Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• antmicro / openssd-nvme
  ☆19Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆62Updated 5 months ago
• arpitp / ssd-controller
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆14Updated 10 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆46Updated last year
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆26Updated last year
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆22Updated 4 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 4 years ago
• antmicro / nvme-verilog-pcie
  ☆58Updated 2 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 4 months ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆37Updated 3 years ago
• rsarwar87 / xdma_dsc_byp_cltr
  VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe
  ☆15Updated 5 years ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆15Updated 6 years ago
• DUNE / pl-nvme
  ☆28Updated 4 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆33Updated 9 years ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• alexforencich / dma-bench
  ☆25Updated 2 years ago
• corundum / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆20Updated last year
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆42Updated last year
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago