papcjy / mnist_fpgaLinks
using xilinx xc6slx45 to implement mnist net
☆83Updated 7 years ago
Alternatives and similar repositories for mnist_fpga
Users that are interested in mnist_fpga are comparing it to the libraries listed below
Sorting:
- hls code zynq 7020 pynq z2 CNN☆86Updated 6 years ago
- 中文:☆104Updated 5 years ago
- it is a set for all the respository of the project.☆99Updated 6 years ago
- FPGA☆158Updated last year
- PYNQ学习资料☆171Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆102Updated last year
- ☆55Updated 2 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆239Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- FPGA Accelerator for CNN using Vivado HLS☆325Updated 4 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Implement Tiny YOLO v3 on ZYNQ☆299Updated 6 months ago
- A DNN Accelerator implemented with RTL.☆67Updated 9 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆188Updated last year
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- ☆48Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆242Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- HLS_YOLOV3☆25Updated last year
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆186Updated 8 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- CNN acceleration on virtex-7 FPGA with verilog HDL☆463Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA实现动态图像识别☆23Updated 5 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago