A Voila-Jones face detector hardware implementation
☆33Nov 29, 2018Updated 7 years ago
Alternatives and similar repositories for face_detect_open
Users that are interested in face_detect_open are comparing it to the libraries listed below
Sorting:
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- AXI memory-mapped VGA module originally designed for the Avent Zedboard☆16Aug 2, 2016Updated 9 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Jan 10, 2018Updated 8 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆16Dec 9, 2018Updated 7 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆23Nov 7, 2022Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated last month
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆44Feb 17, 2019Updated 7 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆250Dec 29, 2018Updated 7 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- Implementation of the PCIe physical layer☆61Jul 11, 2025Updated 7 months ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Apr 24, 2019Updated 6 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- ☆21Jun 17, 2014Updated 11 years ago
- 4通道CMOS相机上位机项目描述:硬件FPGA进行CMOS图像采集,通过网络传输数据,然后在PC上实现4通道CMOS图像显示;上位机可以通过界面 操作完成对相机的控制。☆28Jul 21, 2018Updated 7 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 4 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- Automatically exported from code.google.com/p/lxyppc-serial☆25Jul 30, 2019Updated 6 years ago
- GUI Builder for littlevgl.☆24Sep 13, 2021Updated 4 years ago
- ☆78Feb 5, 2022Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Feb 24, 2026Updated last week
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 8 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- ☆35Mar 10, 2021Updated 4 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Documents for ARM☆35May 8, 2025Updated 9 months ago