A Voila-Jones face detector hardware implementation
☆33Nov 29, 2018Updated 7 years ago
Alternatives and similar repositories for face_detect_open
Users that are interested in face_detect_open are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AXI memory-mapped VGA module originally designed for the Avent Zedboard☆16Aug 2, 2016Updated 9 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆16Dec 9, 2018Updated 7 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Apr 24, 2019Updated 6 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.☆15Feb 26, 2018Updated 8 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆253Dec 29, 2018Updated 7 years ago
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated 2 months ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆44Feb 17, 2019Updated 7 years ago
- Automatically exported from code.google.com/p/lxyppc-serial☆25Jul 30, 2019Updated 6 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- ☆79Feb 5, 2022Updated 4 years ago
- ☆14Aug 1, 2023Updated 2 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Mar 10, 2026Updated 2 weeks ago
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆12Apr 15, 2023Updated 2 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- Video converter based on Lattice CrossLink-NX☆18Dec 11, 2025Updated 3 months ago
- This is a GCS based on C# for Windows7/10, which is forked and modified from https://github.com/ArduPilot/MissionPlanner☆18May 30, 2023Updated 2 years ago
- Some useful documents of Synopsys☆95Nov 5, 2021Updated 4 years ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆34Feb 19, 2026Updated last month
- ☆23Dec 7, 2019Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 5 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Jan 18, 2021Updated 5 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 5 years ago
- A Common frame for menu☆12Mar 6, 2018Updated 8 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago