suisuisi / FPGAandCNN
基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
☆263Updated last year
Related projects: ⓘ
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆356Updated 3 years ago
- FPGA project☆193Updated 2 years ago
- ☆175Updated 5 months ago
- FPGA☆137Updated 2 months ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆478Updated 6 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆126Updated 4 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆184Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆246Updated 2 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆58Updated 2 years ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆108Updated 5 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆123Updated last year
- FPGA实现简单的图像处理算法☆30Updated last year
- 2023集创赛紫光同创杯一等奖项目☆56Updated 8 months ago
- ☆230Updated 6 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆155Updated 5 months ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆59Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆23Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆208Updated 5 years ago
- 一个开源的FPGA神经网络加速器。☆104Updated last year
- FPGA-Edge-Detection-Project1☆48Updated 2 years ago
- 在FPGA中将图像数据输入到DDR3中,再输送到HDMI接口上进行显示。☆19Updated last year
- FPGA☆111Updated 4 years ago
- PYNQ学习资料☆153Updated 4 years ago
- ☆112Updated this week
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆51Updated last year
- some interesting demos for starters☆59Updated last year
- 数字IC设计 学习笔记☆110Updated 2 years ago
- image processing based FPGA☆94Updated 3 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆171Updated 6 years ago
- CNN acceleration on virtex-7 FPGA with verilog HDL☆398Updated 6 years ago