flymin / LeNet-on-ZynqLinks
Simulating implement of LeNet network on Zynq-7020 FPGA
☆28Updated 6 years ago
Alternatives and similar repositories for LeNet-on-Zynq
Users that are interested in LeNet-on-Zynq are comparing it to the libraries listed below
Sorting:
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- ☆65Updated 6 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆60Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆10Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- FFT generator using Chisel☆62Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- ☆36Updated 10 years ago
- ☆34Updated 6 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- Hardware accelerator for convolutional neural networks☆52Updated 3 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago