flymin / LeNet-on-ZynqLinks
Simulating implement of LeNet network on Zynq-7020 FPGA
☆28Updated 6 years ago
Alternatives and similar repositories for LeNet-on-Zynq
Users that are interested in LeNet-on-Zynq are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- ☆65Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- ☆10Updated 5 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- ☆34Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- FFT generator using Chisel☆61Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- AXI总线连接器☆100Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago