flymin / LeNet-on-Zynq
Simulating implement of LeNet network on Zynq-7020 FPGA
☆28Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for LeNet-on-Zynq
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆36Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆24Updated 5 years ago
- An LeNet RTL implement onto FPGA☆39Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆44Updated 6 years ago
- FFT generator using Chisel☆56Updated 3 years ago
- ☆60Updated 5 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆36Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆69Updated 2 years ago
- hls code zynq 7020 pynq z2 CNN☆77Updated 5 years ago
- ☆43Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- fpga跑sobel识别算法☆26Updated 3 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆20Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- 中文:☆92Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- AXI总线连接器☆91Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- ☆93Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago