KastnerRG / cgra4mlLinks
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
☆101Updated 3 weeks ago
Alternatives and similar repositories for cgra4ml
Users that are interested in cgra4ml are comparing it to the libraries listed below
Sorting:
- NeuraLUT-Assemble☆46Updated 4 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- IC implementation of TPU☆144Updated 6 years ago
- ☆71Updated 7 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- ☆40Updated 6 years ago
- ☆61Updated 8 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆46Updated last month
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- ☆64Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- ☆46Updated last year
- ☆65Updated 8 months ago
- Library of approximate arithmetic circuits☆61Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆196Updated 5 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆159Updated 10 months ago
- AMD University Program HLS tutorial☆123Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated this week
- Verilog Implementation of 32-bit Floating Point Adder☆44Updated 5 years ago