Implementation of CNN using Verilog
☆249Oct 13, 2017Updated 8 years ago
Alternatives and similar repositories for Convolutional-Neural-Network
Users that are interested in Convolutional-Neural-Network are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A convolutional neural network implemented in hardware (verilog)☆166Sep 7, 2017Updated 8 years ago
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆199Mar 20, 2024Updated 2 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆590Jun 18, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- CNN acceleration on virtex-7 FPGA with verilog HDL☆487Feb 27, 2018Updated 8 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆262Dec 29, 2018Updated 7 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆188Jan 28, 2017Updated 9 years ago
- Convolutional Neural Network RTL-level Design☆86Oct 22, 2021Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆257Apr 10, 2023Updated 3 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆167Dec 13, 2020Updated 5 years ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆313Sep 7, 2022Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware accelerator for convolutional neural networks☆76Aug 9, 2022Updated 3 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- System Verilog code describing a fully combinational binarized neural network.☆36Jul 6, 2018Updated 8 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆200Dec 15, 2017Updated 8 years ago
- CNN accelerator☆30Jun 11, 2017Updated 9 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆605Feb 19, 2021Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 11 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆20Aug 6, 2025Updated 11 months ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 5 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 7 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆108Dec 14, 2023Updated 2 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆35Dec 26, 2023Updated 2 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆31Feb 21, 2024Updated 2 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆15May 17, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆190Jun 20, 2024Updated 2 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆62Feb 10, 2026Updated 5 months ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- An LeNet RTL implement onto FPGA☆50May 4, 2018Updated 8 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- IC implementation of Systolic Array for TPU☆367Oct 21, 2024Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆453Dec 2, 2019Updated 6 years ago