ZFTurbo / MobileNet-in-FPGA
Generator of verilog description for FPGA MobileNet implementation
☆146Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for MobileNet-in-FPGA
- Verilog Generator of Neural Net Digit Detector for FPGA☆291Updated 2 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆66Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆86Updated 10 months ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆261Updated 4 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆67Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆158Updated 7 months ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- ☆242Updated 4 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆88Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆51Updated 2 years ago
- A convolutional neural network implemented in hardware (verilog)☆151Updated 7 years ago
- Verilog Convolutional Neural Network on PYNQ☆27Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆77Updated 5 years ago
- DPU on PYNQ☆202Updated 9 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆119Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆106Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- FPGA Accelerator for CNN using Vivado HLS☆297Updated 3 years ago
- ☆31Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- verilog CNN generator for FPGA☆32Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆172Updated 7 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆110Updated 3 years ago