ZFTurbo / MobileNet-in-FPGALinks
Generator of verilog description for FPGA MobileNet implementation
☆173Updated 3 years ago
Alternatives and similar repositories for MobileNet-in-FPGA
Users that are interested in MobileNet-in-FPGA are comparing it to the libraries listed below
Sorting:
- Verilog Generator of Neural Net Digit Detector for FPGA☆311Updated 2 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆73Updated 7 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆95Updated last year
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆278Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆160Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- ☆248Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- PYNQ, Neural network Language model, Overlay☆109Updated 6 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆183Updated 8 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆142Updated 7 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆261Updated 2 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆33Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆90Updated 5 years ago
- DPU on PYNQ☆225Updated last week
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago