lowRISC / ibex-demo-system

Related projects ⓘ

Alternatives and complementary repositories for ibex-demo-system

• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 8 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆140Updated this week
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆82Updated 6 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆68Updated 10 years ago
• chipsalliance / uvm-verilator
  ☆75Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆43Updated 3 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆36Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆123Updated this week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆83Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆48Updated 5 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆148Updated this week
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆84Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆74Updated 10 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆69Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 5 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆58Updated 3 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆108Updated this week
• accellera-official / uvm-core
  ☆57Updated 2 months ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week