Alternatives and similar repositories for ibex-demo-system

Users that are interested in ibex-demo-system are comparing it to the libraries listed below

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆182Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 2 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆164Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 11 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆247Updated this week
• chipsalliance / uvm-verilator
  ☆110Updated 3 weeks ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆161Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last week
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆72Updated 4 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆155Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆219Updated 8 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated last year
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆97Updated 3 months ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆98Updated 5 months ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆104Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆114Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆126Updated 2 weeks ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆181Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated 2 months ago
• accellera-official / uvm-core
  ☆100Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 3 weeks ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆169Updated 3 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆228Updated this week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆55Updated 5 years ago