Alternatives and similar repositories for GraphLily:

Users that are interested in GraphLily are comparing it to the libraries listed below

• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆86Updated 5 months ago
• cornell-zhang / UniSparse
  Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization
  ☆30Updated 4 months ago
• cornell-zhang / SPADE
  ☆11Updated 3 years ago
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 10 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 6 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated last week
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆71Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆63Updated 3 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆17Updated 7 months ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• Xtra-Computing / ReGraph
  Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
  ☆17Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆27Updated this week
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 5 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 3 years ago
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• sharc-lab / GenGNN
  ☆36Updated 3 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆31Updated last week
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆47Updated 3 weeks ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆13Updated 6 months ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 7 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• UIUC-ChenLab / Nimblock
  ☆11Updated last year
• pnnl / arena
  The programming runtime and interfaces for ARENA.
  ☆14Updated 3 years ago