Alternatives and similar repositories for GraphLily:

Users that are interested in GraphLily are comparing it to the libraries listed below

• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 6 months ago
• cornell-zhang / UniSparse
  Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization
  ☆30Updated 5 months ago
• cornell-zhang / SPADE
  ☆11Updated 3 years ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated 2 weeks ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 7 months ago
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 11 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• sfu-arch / SpGEMM
  ☆35Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆78Updated 8 months ago
• cornell-zhang / quickest
  QuickEst repository: Quick Estimation of Quality of Results
  ☆26Updated 6 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆18Updated 8 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 7 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆48Updated 3 weeks ago
• sharc-lab / GenGNN
  ☆36Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆71Updated 2 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆20Updated 2 years ago
• cornell-zhang / GLAIVE
  Graph-learning assisted instruction vulnerability estimation published in DATE 2020
  ☆13Updated 4 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated this week
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆73Updated 3 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆44Updated 3 weeks ago
• hngenc / stellar
  ☆26Updated 5 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago