kmisimn76 / SparseAccelLinks
CNN simd based accelerator using Vitis HLS
☆10Updated 3 years ago
Alternatives and similar repositories for SparseAccel
Users that are interested in SparseAccel are comparing it to the libraries listed below
Sorting:
- Open-source of MSD framework☆16Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆24Updated 6 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆119Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆18Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆17Updated 4 months ago
- ☆17Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆45Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆64Updated 2 weeks ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆95Updated 8 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆11Updated last year
- ☆72Updated 2 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆35Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- ☆35Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago