kmisimn76 / SparseAccelLinks
CNN simd based accelerator using Vitis HLS
☆10Updated 3 years ago
Alternatives and similar repositories for SparseAccel
Users that are interested in SparseAccel are comparing it to the libraries listed below
Sorting:
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- Open-source of MSD framework☆16Updated 2 years ago
- ☆19Updated 6 months ago
- Collection of kernel accelerators optimised for LLM execution☆25Updated last week
- ☆20Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆121Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆46Updated last year
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated 3 weeks ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- ☆71Updated 6 years ago
- Model LLM inference on single-core dataflow accelerators☆16Updated this week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆106Updated 10 months ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆72Updated 2 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆68Updated 10 months ago
- ☆35Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year