hatsu3 / Sanger
☆43Updated 3 years ago
Alternatives and similar repositories for Sanger:
Users that are interested in Sanger are comparing it to the libraries listed below
- A co-design architecture on sparse attention☆50Updated 3 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆25Updated last year
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆39Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆50Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- ☆24Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆78Updated 2 weeks ago
- ☆26Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last month
- ☆34Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆26Updated 2 weeks ago
- ViTALiTy (HPCA'23) Code Repository☆21Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆65Updated last month
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆29Updated 10 months ago
- ☆39Updated 9 months ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆84Updated 7 months ago
- ☆27Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 8 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆126Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆83Updated 11 months ago
- ☆93Updated last year
- Eyeriss chip simulator☆36Updated 5 years ago
- ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write …☆19Updated 8 years ago