UCLA-VAST / heterohalide
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
☆13Updated 4 years ago
Related projects: ⓘ
- ☆22Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 3 weeks ago
- Domain-Specific Architecture Generator 2☆20Updated last year
- DASS HLS Compiler☆26Updated 11 months ago
- ☆12Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- ☆31Updated 3 years ago
- ☆17Updated last year
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆11Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- ☆11Updated last month
- A graph linear algebra overlay☆47Updated last year
- A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.☆11Updated 6 months ago
- A Generic Distributed Auto-Tuning Infrastructure☆21Updated 3 years ago
- ☆27Updated 5 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆13Updated 5 months ago
- Accelerating SSSP for power-law graphs using an FPGA.☆21Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆34Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆13Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆19Updated last month
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆18Updated 7 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆31Updated 4 months ago
- Polyhedral High-Level Synthesis in MLIR☆27Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆55Updated last month