Alternatives and similar repositories for heterohalide

Users that are interested in heterohalide are comparing it to the libraries listed below

• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 7 months ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 4 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆24Updated 9 months ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆33Updated 2 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆16Updated 3 years ago
• Yu-Maryland / Differentiable_Scheduler_ICML24
  Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
  ☆20Updated 10 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 2 months ago
• Xilinx / hydra
  ☆13Updated 3 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆29Updated 2 years ago
• zjru / COMBA
  A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
  ☆37Updated 4 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated last year
• Blaok / fpga-runtime
  ☆12Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆14Updated last year
• he-actlab / polymath
  ☆22Updated 6 months ago
• suchandler96 / gem5-NVDLA
  ☆34Updated 5 months ago
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆22Updated 2 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆44Updated 5 months ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆14Updated 2 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆31Updated last year