NeuraChip Accelerator Simulator
☆16Apr 26, 2024Updated last year
Alternatives and similar repositories for neurachip
Users that are interested in neurachip are comparing it to the libraries listed below
Sorting:
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- HW accelerator mapping optimization framework for in-memory computing☆28Jun 3, 2025Updated 9 months ago
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- Arrow Matrix Decomposition - Communication-Efficient Distributed Sparse Matrix Multiplication☆15Mar 25, 2024Updated last year
- ☆14Apr 8, 2025Updated 10 months ago
- ☆13Nov 1, 2021Updated 4 years ago
- RTL generator for SpGEMM☆10Feb 2, 2021Updated 5 years ago
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- Implementation of FusedMM method for IPDPS 2021 paper titled "FusedMM: A Unified SDDMM-SpMM Kernel for Graph Embedding and Graph Neural N…☆31Aug 12, 2022Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- ☆19Mar 21, 2023Updated 2 years ago
- ☆20Feb 12, 2025Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ☆16Apr 10, 2023Updated 2 years ago
- ☆24Apr 13, 2025Updated 10 months ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Mar 30, 2022Updated 3 years ago
- ☆72Mar 22, 2020Updated 5 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Mar 20, 2025Updated 11 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆75Dec 19, 2022Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated last year
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆40Oct 31, 2022Updated 3 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Jul 26, 2024Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆24Nov 8, 2024Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48May 21, 2022Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆58Nov 22, 2023Updated 2 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆27Dec 18, 2024Updated last year
- SST Structural Simulation Toolkit Parallel Discrete Event Core and Services☆193Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆114Jan 4, 2023Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆77Feb 26, 2026Updated last week
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 3 years ago