Alternatives and similar repositories for GraphACT

Users that are interested in GraphACT are comparing it to the libraries listed below

• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆14Updated last year
• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆18Updated 3 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago
• SFU-HiAccel / CHIP-KNN
  [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
  ☆18Updated last year
• ic-lab-duth / FusedGCN4HLS
  Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
  ☆22Updated 3 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆22Updated 10 months ago
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆15Updated last year
• sharc-lab / DGNN-Booster
  ☆16Updated 2 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆52Updated 8 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆58Updated 11 months ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 5 months ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆27Updated 4 years ago
• jasonlin316 / Systolic-Array-for-Smith-Waterman
  This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …
  ☆27Updated 6 years ago
• gicLAB / SECDA
  ☆25Updated 2 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆14Updated last year
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• UT-LCA / tpu_v2
  ☆12Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆31Updated 6 years ago
• PSCLab-ASU / Systolic-CNN
  ☆17Updated 4 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆28Updated last year
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆11Updated 3 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆40Updated this week
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆30Updated 2 years ago