pgroupATusc / GraphACT
Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
☆10Updated 4 years ago
Alternatives and similar repositories for GraphACT:
Users that are interested in GraphACT are comparing it to the libraries listed below
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago
- ☆24Updated 5 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆19Updated 2 months ago
- An HBM FPGA based SpMV Accelerator☆12Updated 5 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆27Updated 3 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated 11 months ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆17Updated 9 months ago
- ☆33Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆28Updated 2 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- ☆18Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- ☆16Updated last year
- ☆3Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆22Updated 5 years ago
- ☆9Updated 2 years ago
- ☆33Updated 5 years ago
- ☆15Updated 3 years ago
- NeuraChip Accelerator Simulator☆11Updated 9 months ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Template for project1 TPU☆13Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 6 months ago
- ☆33Updated this week
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago