UCLA-VAST / splagLinks
Accelerating SSSP for power-law graphs using an FPGA.
☆23Updated 3 years ago
Alternatives and similar repositories for splag
Users that are interested in splag are comparing it to the libraries listed below
Sorting:
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆24Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- ☆10Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- ☆72Updated 2 years ago
- ☆13Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- ☆36Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ACM TODAES Best Paper Award, 2022☆32Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 4 years ago
- ☆16Updated 3 years ago
- ☆25Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆60Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25Updated 6 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆32Updated last year