Alternatives and similar repositories for HiSpMV

Users that are interested in HiSpMV are comparing it to the libraries listed below

• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆51Updated 3 years ago
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆29Updated last year
• hatsu3 / Sanger
  ☆49Updated 3 years ago
• scalesim-project / scale-sim-v3
  ☆29Updated 2 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 2 years ago
• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆45Updated 3 months ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆19Updated last year
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆85Updated 3 months ago
• lsq314 / SpMM_TCAD
  ☆17Updated 10 months ago
• abdelfattah-lab / BitMoD-HPCA-25
  ☆47Updated 2 weeks ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆81Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆60Updated 4 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆56Updated 4 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆94Updated 10 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆69Updated 4 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆57Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆108Updated 5 years ago
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆30Updated 2 weeks ago
• scale-snu / attacc_simulator
  ☆77Updated last year
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆51Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 4 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆38Updated 2 months ago
• maestro-project / gamma
  ☆41Updated last year
• pku-liang / TENET
  An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…
  ☆86Updated last year
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆42Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆17Updated 4 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆100Updated 11 months ago