SFU-HiAccel / HiSpMV
[FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
☆12Updated 2 months ago
Alternatives and similar repositories for HiSpMV:
Users that are interested in HiSpMV are comparing it to the libraries listed below
- A co-design architecture on sparse attention☆51Updated 3 years ago
- ☆16Updated 7 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last month
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- ☆48Updated 3 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆50Updated last month
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 8 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆78Updated 2 weeks ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆65Updated last month
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆43Updated 3 years ago
- ☆26Updated 5 months ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆11Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆14Updated 9 months ago
- ☆39Updated 9 months ago
- ☆28Updated 4 months ago
- ☆26Updated 4 months ago
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆51Updated 4 months ago
- ☆64Updated 9 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆13Updated 2 months ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- ☆26Updated 2 weeks ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆8Updated 2 weeks ago