SFU-HiAccel / HiSpMV
[FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
☆12Updated 2 months ago
Alternatives and similar repositories for HiSpMV:
Users that are interested in HiSpMV are comparing it to the libraries listed below
- A co-design architecture on sparse attention☆52Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- ☆16Updated 7 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated last month
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 9 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆31Updated 4 months ago
- ☆50Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆53Updated 4 months ago
- ☆29Updated 4 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆11Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated last month
- ☆45Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 9 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last week
- ☆39Updated 10 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆30Updated 11 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- Open-source of MSD framework☆16Updated last year
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆35Updated last month
- ☆66Updated 10 months ago
- ☆27Updated 6 months ago
- ☆26Updated last month
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆11Updated last month