AlbertoParravicini / approximate-spmv-topk
Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"
☆14Updated 3 years ago
Alternatives and similar repositories for approximate-spmv-topk:
Users that are interested in approximate-spmv-topk are comparing it to the libraries listed below
- ☆40Updated 10 months ago
- Serpens is an HBM FPGA accelerator for SpMV☆17Updated 5 months ago
- ☆23Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆11Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆19Updated 2 months ago
- ☆25Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆77Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated last month
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆75Updated 5 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 3 years ago
- ☆33Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆47Updated this week
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆13Updated 3 months ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- NeuraChip Accelerator Simulator☆11Updated 8 months ago
- ☆16Updated 2 years ago
- RTL generator for SpGEMM☆9Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆39Updated 8 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- ☆23Updated 3 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 9 months ago
- agile hardware-software co-design☆47Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆27Updated 5 months ago
- ☆25Updated 8 months ago
- ☆21Updated 2 months ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆33Updated last year