zhuzhzh / verilog_emacsauto.vimView external linksLinks
verilog filetype plugin to enable emacs verilog-mode autos
☆25Apr 24, 2022Updated 3 years ago
Alternatives and similar repositories for verilog_emacsauto.vim
Users that are interested in verilog_emacsauto.vim are comparing it to the libraries listed below
Sorting:
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 3 years ago
- SystemVerilog syntax highlight/indent support in vim☆52Jul 10, 2024Updated last year
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆281Jan 18, 2026Updated 3 weeks ago
- UVM verification kits which uses YASA as simulation script☆17Dec 10, 2019Updated 6 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆413Oct 13, 2024Updated last year
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- The source code of blog☆14Dec 12, 2021Updated 4 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated last year
- SystemVerilog vim scripts☆70Jan 25, 2023Updated 3 years ago
- Spike with a coherence supported cache model☆14Jul 9, 2024Updated last year
- ☆14Nov 5, 2017Updated 8 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- automatic-verilog based on vimscript☆283Oct 24, 2023Updated 2 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- System verilog register model for uvm testbenches.☆21Aug 29, 2018Updated 7 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- ☆23Oct 8, 2019Updated 6 years ago
- UVM VIP architecture generator☆20Aug 24, 2020Updated 5 years ago
- DUTH RISC-V Microprocessor☆23Dec 4, 2024Updated last year
- A generic class library in SystemVerilog☆87May 20, 2021Updated 4 years ago
- use pivpi to drive testbench event☆21Jul 21, 2016Updated 9 years ago
- AMC: Asynchronous Memory Compiler☆52Jun 29, 2020Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆145Jan 23, 2024Updated 2 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆29Nov 3, 2025Updated 3 months ago
- Generate UVM register model from compiled SystemRDL input☆60Nov 25, 2025Updated 2 months ago
- Download proccedings from DVCon☆22Jun 9, 2021Updated 4 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆61Jan 16, 2026Updated last month
- ☆11May 31, 2016Updated 9 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆24Jul 17, 2025Updated 6 months ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- UVM interactive debug library☆35May 11, 2017Updated 8 years ago
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 4 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 3 years ago
- Yet Another Simulation Architecture☆79Sep 17, 2020Updated 5 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- ☆10Mar 18, 2020Updated 5 years ago