A simple AXI4 DMA unit written in SpinalHDL.
☆18Apr 18, 2020Updated 6 years ago
Alternatives and similar repositories for DmaUnit
Users that are interested in DmaUnit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- A set of audio processing functions implemented by FPGA☆30Sep 28, 2021Updated 4 years ago
- ☆19Aug 27, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 8 months ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- ☆11Jun 9, 2022Updated 3 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 3 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- ☆24May 6, 2023Updated 2 years ago
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- An out-of-order processor that supports multiple instruction sets.☆22Aug 23, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆22May 6, 2024Updated last year
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 4 years ago
- ☆24Oct 1, 2022Updated 3 years ago
- Getting Started with Triton: A Tutorial for Python Beginners☆52Mar 26, 2026Updated last month
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Apr 16, 2026Updated 2 weeks ago
- SpinalHDL - Cryptography libraries☆60Jul 19, 2024Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A wrapper around Minecraft Raspberry Pi to get it working on Novena☆10Sep 25, 2013Updated 12 years ago
- The sources of the online SpinalHDL doc☆31Updated this week
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 7 years ago
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- MCP server that holds vivado and allows access to vivado without starting a new batch command every time☆31Feb 19, 2026Updated 2 months ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆36Jan 2, 2024Updated 2 years ago
- Grand unified collection of headers to access various hardware chips and components☆19Aug 19, 2015Updated 10 years ago
- Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)☆11Jul 29, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Mar 27, 2026Updated last month
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆29Mar 3, 2024Updated 2 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- ☆12Feb 15, 2024Updated 2 years ago