understanding of cocotb （In Chinese Only）
☆22Jun 10, 2025Updated last year
Alternatives and similar repositories for cocotb_primer
Users that are interested in cocotb_primer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆20Sep 26, 2024Updated last year
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 4 years ago
- ☆29Dec 15, 2025Updated 7 months ago
- ☆20Mar 18, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- AXI interface modules for Cocotb☆344Mar 13, 2026Updated 4 months ago
- Example designs for FPGA Drive FMC☆297Jul 7, 2026Updated 2 weeks ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆19Updated this week
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Updated this week
- UART models for cocotb☆35Sep 7, 2025Updated 10 months ago
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 3 years ago
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 3 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆37Apr 11, 2022Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆23Feb 15, 2023Updated 3 years ago
- Various Notes and Tutorials☆37Sep 9, 2024Updated last year
- A Programmable Hardware Architecture for Network Transport Logic☆38Oct 26, 2021Updated 4 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆20Mar 28, 2026Updated 3 months ago
- Audio filtering with pyfda and cocotb☆13Sep 24, 2020Updated 5 years ago
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆24Oct 8, 2021Updated 4 years ago
- Implemented The UART with FIFO☆16Jul 4, 2019Updated 7 years ago
- Official implementation of the ICLR'25 paper "QERA: an Analytical Framework for Quantization Error Reconstruction".☆14Feb 4, 2025Updated last year
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆10Apr 19, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- c++ version of ViT☆12Nov 13, 2022Updated 3 years ago
- ☆13Jun 4, 2024Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated 2 years ago
- ☆20Nov 7, 2019Updated 6 years ago
- A terminal text editor written in MoonBit☆10Apr 7, 2025Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- ☆14May 15, 2023Updated 3 years ago
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- ☆17Feb 9, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Research paper list for host networking: in a system view☆10Jan 2, 2025Updated last year
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 months ago
- p4 controller in Rust☆12Feb 22, 2021Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- 基于FPGA量化的人脸口罩检测☆23Aug 24, 2021Updated 4 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- LimeSDR ExtIO Plugin for HDSDR☆16Jul 29, 2020Updated 5 years ago