opensmartnic / cocotb_primerLinks
understanding of cocotb (In Chinese Only)
☆17Updated 3 months ago
Alternatives and similar repositories for cocotb_primer
Users that are interested in cocotb_primer are comparing it to the libraries listed below
Sorting:
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- ☆78Updated 3 years ago
- ☆62Updated 3 years ago
- Verilog Content Addressable Memory Module☆111Updated 3 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Verilog Ethernet Switch (layer 2)☆46Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆59Updated 3 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆44Updated 2 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 3 years ago
- round robin arbiter☆75Updated 11 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- FFT generator using Chisel☆62Updated 3 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆78Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆174Updated 2 weeks ago
- NVMe Controller featuring Hardware Acceleration☆93Updated 4 years ago
- AXI4 BFM in Verilog☆33Updated 8 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- PCI express simulation framework for Cocotb☆174Updated last week
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆138Updated 2 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Updated 5 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago