andreasWallner / spinalStuffLinks
☆15Updated last year
Alternatives and similar repositories for spinalStuff
Users that are interested in spinalStuff are comparing it to the libraries listed below
Sorting:
- Virtual development board for HDL design☆42Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆95Updated last week
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 2 weeks ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated this week
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- Re-coded Xilinx primitives for Verilator use☆50Updated 5 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- FuseSoC standard core library☆150Updated last week
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- ☆26Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 2 weeks ago
- ☆33Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- Fusesoc compatible rtl cores☆15Updated 3 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- RISC-V Nox core☆70Updated 4 months ago