Alternatives and similar repositories for spinalStuff

Users that are interested in spinalStuff are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last month
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 2 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated 2 weeks ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 8 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated 3 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆105Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated last week
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated 2 months ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated last week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 10 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆29Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆123Updated 3 months ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆79Updated 3 years ago