andreasWallner / spinalStuffLinks
☆15Updated last year
Alternatives and similar repositories for spinalStuff
Users that are interested in spinalStuff are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Updated 3 weeks ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Extensible FPGA control platform☆61Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆115Updated last week
- Docker Development Environment for SpinalHDL☆20Updated last year
- Demo SoC for SiliconCompiler.☆62Updated last week
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- FuseSoC standard core library☆151Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- ☆60Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- Framework Open EDA Gui☆73Updated last year
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 3 years ago
- UART models for cocotb☆33Updated 5 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated last month
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- ☆26Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated last week
- Wishbone interconnect utilities☆44Updated last month
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago