GuzTech / shdl6800Links
shdl6800: A 6800 processor written in SpinalHDL
☆25Updated 5 years ago
Alternatives and similar repositories for shdl6800
Users that are interested in shdl6800 are comparing it to the libraries listed below
Sorting:
- Simplified environment for litex☆14Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- ☆27Updated 5 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆31Updated 4 years ago
- PLEASE MOVE TO PAWSv2☆16Updated 3 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 4 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆58Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆65Updated this week
- Experiments with Cologne Chip's GateMate FPGA architecture☆16Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- Utilities for the ECP5 FPGA☆17Updated 4 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆24Updated this week
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Retro computing on the Ulx3s ECP5 FPGA board☆24Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated last year
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 3 years ago
- Miscellaneous ULX3S examples (advanced)☆80Updated 3 months ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago