GuzTech / shdl6800Links
shdl6800: A 6800 processor written in SpinalHDL
☆26Updated 5 years ago
Alternatives and similar repositories for shdl6800
Users that are interested in shdl6800 are comparing it to the libraries listed below
Sorting:
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Use ECP5 JTAG port to interact with user design☆30Updated 3 years ago
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- understanding the tinyfpga bootloader☆24Updated 7 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 2 weeks ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆25Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last week
- ice40 USB Analyzer☆58Updated 4 years ago
- Simplified environment for litex☆14Updated 4 years ago
- crap-o-scope scope implementation for icestick☆20Updated 7 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- FLIX-V: FPGA, Linux and RISC-V☆42Updated last year
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Updated last year
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- USB 1.1 Device IP Core☆21Updated 7 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated 2 years ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14Updated 5 years ago
- Some materials and sample source for RV32 OS projects.☆22Updated 3 years ago
- ☆26Updated 5 years ago