Alternatives and similar repositories for J1Sc

Users that are interested in J1Sc are comparing it to the libraries listed below

• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆92Updated 7 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆49Updated 4 months ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated last year
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• mystorm-org / BlackIce-II
  Software, Firmware and documentation for the myStorm BlackIce-II board
  ☆71Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆48Updated last week
• mattvenn / fpga-sram
  mystorm sram test
  ☆29Updated 8 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆81Updated 5 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆112Updated 2 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 4 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆43Updated 7 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated 2 years ago
• mmicko / fpga101-workshop
  FPGA 101 - Workshop materials
  ☆77Updated 6 years ago