SteffenReith / J1Sc

Related projects: ⓘ

• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆42Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆26Updated this week
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 2 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆35Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆63Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆82Updated 8 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆80Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆51Updated 2 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆69Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆105Updated last month
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆101Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 3 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆119Updated 8 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆83Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated 3 weeks ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆113Updated 8 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆56Updated 5 years ago
• pieter3d / simview
  ☆76Updated 6 months ago