SteffenReith / J1ScLinks
A reimplementation of a tiny stack CPU
☆86Updated 2 years ago
Alternatives and similar repositories for J1Sc
Users that are interested in J1Sc are comparing it to the libraries listed below
Sorting:
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- Tools for FPGA development.☆49Updated 5 months ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 8 months ago
- OpenFPGA☆34Updated 7 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- PicoRV☆43Updated 5 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- A FPGA core for a simple SDRAM controller.☆122Updated 4 years ago
- Yosys Plugins☆22Updated 6 years ago
- Software, Firmware and documentation for the myStorm BlackIce-II board☆72Updated 5 years ago
- Tools and Examples for IcoBoard☆80Updated 4 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- ☆61Updated 2 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- Miscellaneous ULX3S examples (advanced)☆82Updated 7 months ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week