HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
☆116Oct 31, 2023Updated 2 years ago
Alternatives and similar repositories for HDLGen
Users that are interested in HDLGen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- automatic-verilog based on vimscript☆291Oct 24, 2023Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆208Jan 28, 2026Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 25, 2026Updated 2 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- UVM interactive debug library☆36Feb 28, 2026Updated 6 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated 2 months ago
- UVM verification kits which uses YASA as simulation script☆19Dec 10, 2019Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆246Jul 16, 2023Updated 3 years ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆289Updated this week
- Yet Another Simulation Architecture☆78Sep 17, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Scripts for XiangShan☆18Updated this week
- ☆24May 6, 2023Updated 3 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆41Sep 21, 2021Updated 4 years ago
- HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and aut…☆37Oct 28, 2024Updated last year
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Import and export IP-XACT XML register models☆39Nov 5, 2025Updated 9 months ago
- ☆38Aug 24, 2026Updated last week
- ☆247Jun 25, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 6 months ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 3 years ago
- ☆26Jul 22, 2026Updated last month
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆59May 10, 2021Updated 5 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 8 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Medium Access Control layer of 802.15.4☆15Nov 14, 2014Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆77Jul 30, 2021Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆152Jan 23, 2024Updated 2 years ago
- ☆17Jun 5, 2024Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆64Jun 18, 2026Updated 2 months ago
- SystemRDL 2.0 language compiler front-end☆282Apr 10, 2026Updated 4 months ago