AdderNet ResNet20 for cifar10 written in SpinalHDL
☆38Mar 14, 2021Updated 5 years ago
Alternatives and similar repositories for SpinalResNet
Users that are interested in SpinalResNet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆162Sep 29, 2026Updated last week
- SpinalHDL Hardware Math Library☆104Jul 12, 2024Updated 2 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated 2 years ago
- Demo Sources for Learning Spinal HDL☆17Dec 5, 2022Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆56Feb 2, 2026Updated 8 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- A static web ui for llama.cpp server. The llama.cpp chat interface for everyone. base on chatbot-ui☆18Oct 27, 2024Updated last year
- SpinalHDL - Cryptography libraries☆62Jul 19, 2024Updated 2 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆47Jul 31, 2025Updated last year
- SDSoC example projects☆13Mar 13, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Models and examples built with hls4ml☆12Apr 8, 2020Updated 6 years ago
- ☆35Apr 20, 2021Updated 5 years ago
- An out-of-order processor that supports multiple instruction sets.☆23Aug 23, 2022Updated 4 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆16Aug 29, 2021Updated 5 years ago
- Network components (NIC, Switch) for FireBox☆20Oct 27, 2024Updated last year
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- ☆10Jan 3, 2022Updated 4 years ago
- Masked Ascon Software Implementations☆15May 3, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆19Mar 17, 2021Updated 5 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 7 months ago
- ☆14Aug 6, 2020Updated 6 years ago
- Scala based HDL☆2,051Updated this week
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- ☆17Jul 21, 2017Updated 9 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆135Jun 27, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- This repository contains the code for this paper: Chiplet-Gym: An RL-based Optimization Framework for Chiplet-based AI Accelerator☆25Sep 28, 2024Updated 2 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 9 months ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆23May 6, 2024Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog☆30Nov 20, 2018Updated 7 years ago
- LLM Inference with Microscaling Format☆35Nov 12, 2024Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 5 years ago