yportne13 / SpinalResNetLinks
AdderNet ResNet20  for cifar10 written in SpinalHDL
☆35Updated 4 years ago
Alternatives and similar repositories for SpinalResNet
Users that are interested in SpinalResNet are comparing it to the libraries listed below
Sorting:
- eyeriss-chisel3☆41Updated 3 years ago
- ☆70Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆65Updated 3 years ago
- Verilog implementation of Softmax function☆73Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆173Updated 5 years ago
- ☆37Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆135Updated 5 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- A systolic array matrix multiplier☆26Updated 6 years ago
- ☆120Updated 5 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆98Updated 9 months ago
- IC implementation of TPU☆135Updated 5 years ago
- ☆16Updated 5 years ago
- ☆42Updated 4 years ago
- ☆17Updated 5 months ago
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- ☆56Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago