Alternatives and similar repositories for SpinalResNet:

Users that are interested in SpinalResNet are comparing it to the libraries listed below

• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆29Updated 5 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆15Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆88Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆36Updated 2 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆56Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆77Updated 3 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆58Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆139Updated 5 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆57Updated 3 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆44Updated 5 months ago
• chenhaoc / cnnhwpe
  ☆64Updated 2 years ago
• Giftwen / DC_script
  syn script for DC Compiler
  ☆12Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆38Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated last month
• yportne13 / spinalAdderNetMNIST
  SpinalHDL AdderNet MNIST
  ☆11Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆27Updated 4 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆71Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆11Updated 4 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆100Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆40Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago