Alternatives and similar repositories for SpinalResNet

Users that are interested in SpinalResNet are comparing it to the libraries listed below

• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 7 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆112Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆177Updated 6 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆78Updated 3 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• gem5-X / TiC-SAT
  ☆19Updated 7 months ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆62Updated 4 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆156Updated last year
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 6 years ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆60Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆33Updated 4 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆148Updated 7 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆123Updated 5 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆47Updated last year
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆68Updated 11 months ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆144Updated 6 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆29Updated 4 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆92Updated 3 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆110Updated 11 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆76Updated last month
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆74Updated 6 years ago