ZLXT / SpinalHDL-MIPS
Translate the source code of Veriog version to Spinalhdl version
☆10Updated 3 years ago
Alternatives and similar repositories for SpinalHDL-MIPS:
Users that are interested in SpinalHDL-MIPS are comparing it to the libraries listed below
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A Verilog implementation of a processor cache.☆24Updated 7 years ago
- ☆25Updated 4 years ago
- ☆20Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- Educational 16-bit MIPS Processor☆17Updated 5 years ago
- ☆40Updated 5 years ago
- UART 16550 core☆32Updated 10 years ago
- ☆16Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- double_fpu_verilog☆14Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated this week
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- Verilog Code for a JPEG Decoder☆33Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆9Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆26Updated last year
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆11Updated last month
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆26Updated 4 years ago
- PCI Express controller model☆47Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year