Alternatives and similar repositories for SpinalHDL-MIPS:

Users that are interested in SpinalHDL-MIPS are comparing it to the libraries listed below

• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• pulp-platform / fpu
  ☆42Updated 6 years ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆25Updated 7 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated last week
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆27Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆28Updated last year
• RicardoNid / ChainsawOld
  ☆23Updated 2 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 7 months ago
• AmeerAbdelhadi / Switched-Multiported-RAM
  Switched SRAM-based Multi-ported RAM
  ☆15Updated 4 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated 2 months ago
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆19Updated 11 months ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• yportne13 / spinalAdderNetMNIST
  SpinalHDL AdderNet MNIST
  ☆11Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆22Updated 10 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• mfkiwl / E203_dma
  ☆9Updated 4 years ago
• maxs-well / USB_Ctrl
  USB2.0 Verilog
  ☆17Updated 5 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• freecores / mips_16
  Educational 16-bit MIPS Processor
  ☆17Updated 6 years ago