An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.
☆14Jun 5, 2019Updated 6 years ago
Alternatives and similar repositories for sodor-spinal
Users that are interested in sodor-spinal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- A reimplementation of a tiny stack CPU☆87Dec 8, 2023Updated 2 years ago
- ☆19Aug 27, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Jan 7, 2026Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆54Feb 2, 2026Updated 2 months ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 7 months ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- An implementation of RISC-V☆50Dec 11, 2025Updated 4 months ago
- ☆24May 6, 2023Updated 2 years ago
- RISCV lock-step checker based on Spike☆14Mar 6, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- Scala library to support coroutines and generators☆20Apr 3, 2011Updated 15 years ago
- Coq BPF interpreter☆19Jan 18, 2018Updated 8 years ago
- SpinalHDL - Cryptography libraries☆60Jul 19, 2024Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆13Jul 24, 2020Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Clio, ASPLOS'22.☆79Feb 8, 2022Updated 4 years ago
- "My 5-Year IoT Mission" presentation at Hackware 3 Dec 2019☆10Dec 3, 2019Updated 6 years ago
- ☆23Oct 1, 2022Updated 3 years ago
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- A Finite Difference Time Domain (FDTD) simulator written in Rust☆13Apr 17, 2024Updated last year
- ☆11Dec 18, 2017Updated 8 years ago
- a simple header-only json serialization solution for c++ based on picojson☆13Dec 25, 2016Updated 9 years ago
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- This is a clone of an SVN repository at http://svn.code.sf.net/p/edif2kicad/code. It had been cloned by http://svn2github.com/ , but the …☆12Jun 7, 2016Updated 9 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 7 years ago
- This is an implementation of Y86 instruction set in Verilog HDL.☆11Feb 28, 2018Updated 8 years ago
- ☆15Mar 27, 2026Updated 2 weeks ago
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- Julia API for Intan RHD2000☆10Apr 14, 2023Updated 3 years ago