ZiCog / sodor-spinal
An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.
☆14Updated 5 years ago
Alternatives and similar repositories for sodor-spinal:
Users that are interested in sodor-spinal are comparing it to the libraries listed below
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- An implementation of RISC-V☆30Updated 3 weeks ago
- Docker Development Environment for SpinalHDL☆19Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 7 months ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆20Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- matrix-coprocessor for RISC-V☆14Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- ☆38Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago